• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to an optical receiver of an optical link comprising: a photodiode (202) coupled between a detection node (204) and a first supply voltage rail (GND), the photodiode being adapted to receive a signal d optical clock comprising pulses; a switch (206) coupled between the detection node (204) and a second power supply voltage (VDD) rail; a first transistor (211) coupled by its main conduction nodes between the second supply voltage rail (VDD) and a first output node (212) and having its control node coupled to the detection node (204), in wherein the switch (206) is controlled based on a voltage on the first output node (212).
    公开号:FR3033220A1
    申请号:FR1551697
    申请日:2015-02-27
    公开日:2016-09-02
    发明作者:Robert Polster
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD The present description relates to the field of optical communications, and in particular to an optical receiver of an optical link for receiving a clock signal.
    [0002] BACKGROUND OF THE INVENTION Optical links provide high data transmission rates at low power, and thus provide a viable solution for replacing ordinary copper interconnects between integrated circuits. Optical reception is based on capturing, using a photosensitive device such as a photodiode, a light signal which is generally digitally coded, and which can have a power level as low as 10 pW. The photosensitive device for example generates a small current which is converted by the optical receiver into a digital voltage signal. In order to correctly receive the data signal transmitted optically on such an optical link, it is generally necessary to receive a synchronization signal on the optical link. In some embodiments, the synchronization signal may be extracted from the data signal itself, but such solutions tend to be complex to implement. Indeed, the coding of the data will generally cause that the synchronization edge is not present in the data signal for each data bit of data transmitted on the link. Alternative solutions use a separate clock channel to transmit a clock signal. In order to reduce energy consolation, it has been proposed to transmit the clock signal over the optical link as a series of pulses rather than as a clock signal having a duty cycle. 50%. For example, such a technique is described in the publication by A. Bhatnagar et al. entitled "Receiverless detection schemes for optical clock distribution", Proceedings of the SPIE - The International Society for Optical Engineering, July 6, 2004, vol.5359, no.1, 15 p.352-9. According to the technique described in this publication, the optical clock signal is transmitted in the form of two sequences of pulses, each of which is received by a corresponding photodiode and converted into a voltage signal. However, a high load level is required to charge the parasitic capacitances of both photodiodes and to trigger detection by a voltage amplifier. In addition, the two photodiodes lead to a relatively large size of the circuit. There is therefore a need in the art for an optical receiver suitable for receiving a low power optical signal and having reduced power consumption and / or reduced surface area over existing solutions. SUMMARY An object of embodiments of the present disclosure is to at least partially meet one or more needs of the prior art. In one aspect, there is provided an optical receiver of an optical link comprising: a photodiode coupled between a sense node and a first supply voltage rail, the photodiode being adapted to receive a signal of optical clock comprising pulses; a switch coupled between the detection node and a second supply voltage rail; a first transistor coupled by its main conduction nodes between the second supply voltage rail and a first output node and having its control node coupled to the detection node, wherein the switch is controlled on the basis of a voltage on the first output node. According to one embodiment, the switch is coupled to the second supply voltage rail via a voltage shifter. According to one embodiment, the voltage shifting device is a diode-connected transistor. According to one embodiment, the optical receiver further comprises a second transistor coupled by its main conduction nodes between the first output node and the first supply voltage rail and having its control node coupled to the detection node. According to one embodiment, the first output node is coupled to the first supply voltage rail via the series connection of one or more other switches controlled by a clock duty cycle control signal. .
    [0003] According to one embodiment, the series connection of one or more other switches is coupled to the first supply voltage rail via another diode-connected transistor. According to one embodiment, the optical receiver further comprises: a low-pass filter coupled to the first output node; and a comparator adapted to control the switch based on a comparison between an output voltage of the low-pass filter and a threshold level.
    [0004] According to one embodiment, the low-pass filter comprises at least one of the following elements: a variable resistor; and a variable capacitor. According to one embodiment, the low-pass filter is a RC filter comprising a resistor and a transistor coupled in parallel between the first output node and an intermediate node, and a variable capacitor, consisting of a transistor gate, coupled at the intermediate node. According to one embodiment, the threshold voltage is generated by a duty cycle control circuit adapted to adjust the duty cycle of the clock signal. According to one embodiment, the comparator is implemented by an inverter, the threshold level being the threshold voltage of the inverter.
    [0005] According to one embodiment, the optical receiver further comprises a sequence of one or more inverters coupled to the first output node and providing the clock signal. According to one embodiment, the optical receiver further comprises a duty cycle detection circuit comprising: a first low-pass filter coupled to the output of a first inverter of the inverter sequence; a second low-pass filter coupled to the output of a second inverter of the inverter sequence, the outputs of the first and second inverters being separated by an odd number of inverters from the inverter sequence; and a voltage integrator adapted to generate an output voltage as a function of a voltage difference between the output voltages of the first and second low pass filters, the voltage integrator being adapted to control the RC value of the pass filter. low.
    [0006] According to one embodiment, the voltage integrator comprises a current mirror comprising: a first branch passing a first current based on the output voltage of the first low-pass filter; and a second branch comprising a second transistor passing a second current based on the first current, and a third transistor allowing a third current based on the output voltage of the second low pass filter to be passed, an intermediate node between the second and third transistors providing the output voltage of the voltage integrator.
    [0007] According to another embodiment, there is provided a method for receiving a clock signal on an optical link, comprising: receiving, by a photodiode coupled between a detection node and a first supply voltage rail, a optical clock transmission signal; and controlling a switch, coupled between the sense node and a second supply voltage rail, based on a voltage on a first output node, the first output node being coupled by the main conduction nodes of a first transistor to the second supply voltage rail and having its control node coupled to the detection node. Brief Description of the Drawings The above-mentioned and other features and advantages will become apparent from the following detailed description of embodiments, given by way of illustration and not limitation, with reference to optical optical drawings. in the optics 30 in the optical optics joined in which: Figure 1 schematically illustrates a connection according to an exemplary embodiment; Figure 2 schematically illustrates a receiver according to an exemplary embodiment; FIG. 3 represents timing diagrams of circuit signals of FIG. 2 according to an exemplary embodiment; Figure 4 schematically illustrates a receiver according to another embodiment; FIG. 5 shows timing diagrams of circuit signals of FIG. 4 according to an exemplary embodiment; Figure 6 schematically illustrates a receiver according to yet another embodiment; Figure 7 schematically illustrates a receiver according to yet another embodiment; and FIG. 8 illustrates a voltage integrator of the circuit of FIG. 7 in more detail according to an exemplary embodiment. DETAILED DESCRIPTION In the present description, the term "connected" is used to denote a direct connection between two elements, while the term "coupled" is used to designate a connection between two elements which may be direct or intermediate of one or more other components such as resistors, capacitors, or transistors. In addition, as used herein, the term "substantially" is used to refer to a range of +/- 10% of the value in question. FIG. 1 schematically illustrates an optical link 100. As illustrated, on a transmitting side, a data signal D is converted by an optical transmitter (OPTICAL TRANSMITTER) 102 into an optical signal, which is transmitted by the intermediate waveguide 104 to the receiving side of the optical link. On the receiving side, the optical signal is received by an optical receiver (OPTICAL RECEIVER) 106, which converts the optical signal in the other direction to obtain the data signal D. To achieve this, it uses a signal of CLK clock, which is transmitted through a separate clock channel of the optical link. In particular, on the transmit side, a clock signal CLK and converts into an optical signal by another optical transmitter (OPTICAL TRANSMITTER) 108. This optical signal is transmitted by another waveguide 110 to the side of the receiver. reception, where it is received by another optical receiver (OPTICAL RECEIVER) 112, and reconverted to a voltage signal CLK, which is supplied to the optical receiver 106 to allow the optical data signal to be received correctly. The optical receiver 112 uses an "integration and discharge" receiving technique adapted to receiving a clock signal, as will now be described more in detail with reference to FIG. 2. The circuit receives clock pulses, and converts these pulses into a clock signal having a duty cycle of substantially 50% by using a feedback signal to reset the input signal. FIG. 2 schematically illustrates an optical receiver 200 according to an exemplary embodiment. For example, this circuit is used to implement the optical receiver 112 of the optical link of FIG.
    [0008] The circuit 200 comprises a photodiode 202 adapted to receive the optical clock signal consisting of pulses. The photodiode 202 has for example its cathode coupled to a detection node 204 of the receiver, and its anode coupled to ground. The current flowing through photodiode 202 is designated m. The sense node 204 is also coupled through a switch 206 to a supply voltage rail VDD. In the example of FIG. 2, the connector 206 is coupled to VDD via a diode-connected transistor 208, which is, for example, a MOS transistor having its gate coupled to its drain. In alternative embodiments, the collector 206 could be directly connected to the supply voltage VDD rail. The detection node 204 is further coupled to a chain of inverters. For example, the node 204 is coupled to the input of an inverter 210, which provides on its output node 212, a voltage signal VINv. An example of the circuit forming the inverter 210 is illustrated in FIG. 2 and comprises a PMOS transistor 211 and an NMOS transistor 213 coupled in series with each other by their main conduction nodes between the supply voltage VDD and the ground. The control nodes of the transistors 211, 213, are coupled to the detection node 204 and the drains of the transistors 211, 213 are coupled to the output node 212. The output node 212 is in turn coupled to the input 35 of the transistor. an inverter 214, which itself has its output coupled to the input 301 of another inverter 216, which itself has its output coupled to the input of yet another inverter 218. The output of the inverter 218 for example provides the clock signal CLK at the output of the optical receiver 200. The inverters 214, 216, and 218 5 provide for example an amplification. In alternative embodiments, a different number of inverters could be used in the inverter chain, and for example one or more of the inverters could be omitted. The switch 206 is for example controlled on the basis of the voltage signal VINv at the output of the inverter 212. For example, a feedback path comprises a SWITCH CONTROL 220 which generates a signal to control the switch 206 based on the V1NV signal on the node 212. In alternative embodiments, however, the switch 206 could be controlled by the output voltage of any of the other inverters in the chain. In some embodiments, the switch control circuit 220 includes a delay line for delaying the signal 212, for example a delay of between 10 and 50% of the clock period. For example, although not illustrated in FIG. 2, the switch 206 may comprise an NMOS transistor having its gate coupled to the node 212, and coupled by its main conduction nodes between the node 204 and the diode-connected transistor 208. , and / or a PMOS transistor having its gate coupled to the node 212 via an inverter, and coupled by its main conduction nodes between the node 204 and the diode-connected transistor 208. Alternatively, the switch 206 could be implemented by a so-called "boot-strapped" switch. The operation of the optical receiver 200 will now be described in more detail with reference to Fig. 3. Fig. 3 is a timing chart showing examples of the time characteristics of the Ipp photodiode current, the voltage Vpip on the detection node 204, and the voltage VINv on the node 212 of the optical receiver 200. The photodiode current Ipp comprises for example a series of high pulses, corresponding to light pulses transmitted on the clock channel of the optical link. These pulses are for example transmitted at a frequency between 1 Hz and 10 GHz or more. Each pulse is for example relatively short, having for example a duration of 40% or less of the clock period. However, the receivers described herein can operate with any pulse length, and can for example be used to correct a duty cycle of more than 50%. The current level during each high pulse is, for example, between 11A and 100μA.
    [0009] The voltage VpD on the detection node 204 is for example initially high, and descends relatively linearly during each photodiode current pulse while the capacitors associated with the detection node 204 are discharged by the photodiode current Tm.
    [0010] The solid lines representing the signals VpD and Viblv correspond to the case where the diode-connected transistor 208 is absent, and thus the voltage VpD is reset by the switch 206 at the supply voltage level VDD. The voltage VpD is thus initially at VDD, and the voltage VINv 25 is at ground level. During the high pulse of the photodiode current Ipp, the voltage VpD goes down, and when it falls below a threshold level of the inverter 210, equal for example to substantially VDD / 2, the output voltage of the inverter 210 starts to rise. When this voltage has risen sufficiently, for example to substantially VDD / 2, the switch 206 becomes conductive, resetting the voltage VpD on the sense node 204 at the supply voltage level VDD. This again causes the output of the inverter 210 to drop, and the switch 206 to return to the non-conductive state. It will be appreciated that if the switch 206 is directly connected to the power supply rail VDD and the voltage Vpp is thus reset to VDD, the photodiode 202 will pass a relatively high load in order to switch the state of the power supply. inverter 210, in other words to change the output voltage VviNv from a low voltage to a high voltage. By connecting the switch 206 to the VDD supply rail through the diode-connected transistor 208, the lower load level driven by the photodiode 202 is sufficient to switch the state of the inverter 210. Indeed, the dotted curves in FIG. 3 illustrate the case where the diode-connected transistor 208 is present. Since the reset level of the voltage Vpp starts at a lower level VL, the same Ipp photodiode current causes a faster switching of the state of the inverter 210, and thus leads to a reduced power consumption. The transistor connected in diode 208 will reduce the supply voltage VDD of a gate-source voltage VGs, and thus the level VL is for example equal to VDD-VGs. The gate-source voltage VGs is for example equal to the threshold voltage VTH of the transistor 208. The diode-connected transistor 208 is for example a PMOS transistor 211 having the same dimensions as the PMOS transistor of the inverter 210, and thus the voltage VGs is for example substantially equal to the threshold voltage of the PMOS transistor 211.
    [0011] In alternative embodiments, rather than a diode-connected transistor 208, another type of voltage reduction device between VDD and the com-oncator 204 could be used, such as one or more diodes. In some embodiments, the clock signal CLK generated by the optical receiver 200 of Fig. 2 may have an unbalanced duty cycle, in other words high pulses and low pulses which are not equal to the half of the clock period. A solution for bringing the duty cycle of the clock signal to substantially 50% is illustrated in FIG. 4. FIG. 4 schematically illustrates an optical receiver 400 according to another exemplary embodiment, and which, for example, FIG. 1 shows the receiver 112. Many elements of this circuit are identical to those of the receiver 200 of FIG. 2, and these elements have been referenced with the same reference numerals and will not be described again in detail. In the embodiment of FIG. 4, instead of node 212 being directly connected to control switch 206, it is coupled to control switch 206 through a low pass filter and a comparator 402. For example, the low-pass filter comprises a resistor 404 and a capacitor 406 coupled in series between each other between the node 212 and the ground. An intermediate node 408 between the resistor 404 and the capacitor 406 is coupled to a positive input of the comparator 402. A negative input of the comparator 402 receives, for example, a threshold voltage VTH. The output of the comparator 402 controls the switch 206. In operation, the comparator 402 for example resets the switch 206 only when the voltage VLp at the intermediate node 408 exceeds the threshold voltage VTH. The voltage VLp will rise following the rising edge of the voltage ViNv at a rate based on the time constant of the low pass filter, thereby introducing a delay which provides stability during the reset operation. In the embodiment of FIG. 4, the low-pass filter has a fixed RC value. The delay between the amount of the voltage VINv and the activation of the switch 206 can thus be controlled by the level of the threshold voltage V THRESH. For example, the threshold voltage VTHRESH is generated by a duty cycle control circuit (not shown in FIG. 4) adapted to adjust the duty cycle of the clock signal. Fig. 5 is a timing diagram illustrating the signals Ipp, VpD, VINv, V.Lp and the current DIODE in the diode-connected transistor 208 of Fig. 4 according to an exemplary embodiment. As illustrated, the voltage VpD on the node 204 is not reset as soon as the voltage VINv goes high. Instead, the voltage is reset only when the voltage VLp exceeds the threshold voltage VTH, with a delay tLp after the voltage ViNv has started to rise. FIG. 6 illustrates an optical receiver '600 according to yet another exemplary embodiment, which for example implements the receiver 112 of FIG. 1. The elements common with those of the embodiment of FIG. 4 have been noted with 10 same numerical references, and will not be described again in detail. In the circuit 600, the PMOS transistor 211 of the inverter 210 is present, but the NMOS transistor 213 of this inverter has been removed, and is replaced by switches 602 and 604 coupled in series between the node 212 and the ground, to reset the voltage on the node 212 to a low voltage level. In the example of FIG. 6, a diode-mounted NMOS transistor 606 is also coupled between the switch 604 and the ground, so that the voltage on the node 212 is reset to a level equal to the voltage VGs of the transistor 606. , equal to the threshold voltage VTH of the transistor. In alternative embodiments, the diode-connected transistor 606 could be omitted, or replaced by another type of voltage shifter, such as one or more diodes. One advantage of removing the NMOS transistor 213 from the inverter 210 is that the capacity on the node 204 will be reduced, which implies a greater reduction in the charge to be carried by the photodiode 202 in order to change the state of the VINv voltage. In the optical receiver 600, the comparator 402 of FIG. 4 is implemented by an inverter. In particular, an intermediate node 608 between the switches 602 and 604 is coupled by an inverter 610 to control the switch 206. The voltage on the output of the inverter 610 is also used to control the switches 602 and 604. In the example of FIG. 6, a pulse elongation device 612 is coupled to the output of the inverter 610 and generates a duty cycle control signal -CS to control the switches 602. 604 on the basis of the output voltage of inverter 610. In addition, the low-pass filter of FIG. 4 is replaced in FIG. 6 by a variable low-pass filter consisting of a variable resistor 614. series with a variable capacitor 616, coupled between the node 212 and the ground. An intermediate node between these components is coupled to node 608.
    [0012] The variable resistor 614 and the variable capacitor are for example controlled by one or more control signals (not shown in Fig. 6) to adjust the duty cycle to an appropriate level. For example, the variable resistor 614 could have an analogically controlled resistor, or a digital control signal. Similarly, the variable capacitor 616 could have an analogically controlled capacitance, or a digital control signal. In some embodiments, only one of the components 614, 616 could be variable, and the other have a fixed capacitance or resistance. In operation, initially the output of the inverter 610 is high, the switches 602 and 604 are non-conductive, and the voltage VFB on the intermediate node 608 is equal to the threshold voltage VTH of the transistor 606. When the voltage VINv on the node 212 mounts, the voltage VFB on the intermediate node 608 will also rise until the output of the inverter 610 goes low, which in this example makes the switch 206 conductive to reset the voltage VpD . Further, in response to the downward voltage on the output of the inverter 610, the device 612 will turn on the switches 602, 604 for a period of time to reset the voltage ViNv at the threshold voltage VTH of the transistor 606. This will also bring the voltage VE-13 back to the intermediate node at the threshold voltage VTH of the transistor 606, causing the output of the inverter 610 to return to the state of change. high, and making the switch 206 again non-conductive. The resistance of the variable resistor 614 and / or the capacitance of the variable capacitor 616 are, for example, adjusted in order to obtain the appropriate delay between a rising edge on the node 212 and the falling edge on the output of the inverter 610. FIG. 7 illustrates an optical receiver 700 according to yet another embodiment, which for example implements the receiver 112 of FIG. 1. The elements in common with the embodiment of FIG. 6 have been noted with the same references. digital, and will not be described again in detail. In the embodiment 700, the variable resistor of FIG. 6 is implemented by a resistor 702 of fixed value coupled in parallel with a transistor 704 between the node 212 and the intermediate node 608. In addition, in FIG. the variable capacity device 706 is for example implemented by a transistor gate, for example by a completely depleted silicon-on-insulator transistor (FDSOI) having its gate, which constitutes a node of the capacitor, coupled to the intermediate node 608, and its back gate, its source and its drain connected together to form the other node of the capacitor coupled to the output of a voltage integrator 708. The inputs of the integrator 708 are coupled to a circuit for detecting a discrepancy between the cyclic ratios of the clock signal. This circuit comprises for example a pair of low-pass filters, respectively coupled to two different nodes of the chain of inverters separated by an odd number of inverters, so that one signal is the inverse of the other. For example, a low pass filter consisting of a series connection of a resistor 710 and a capacitor 712 is coupled between the output of the inverter 214 and the ground, and an intermediate node 714 between these components is coupled. at the positive input of the integrator 708. In addition, a low pass filter consisting of a series connection of a resistor 713 and a capacitor 718 is coupled between the output of the resistor and the capacitor 718. the inverter 216 and the ground, and an intermediate node 720 between these components is coupled to the negative input of the integrator 708. The outputs of the inverters 214 and 216 having opposite voltage states, when the duty cycle of the clock is well balanced, the voltages on the intermediate nodes 714 and 720 must be substantially at the same level. Any difference between these voltages indicates a discrepancy in the duty cycle.
    [0013] The integrator 708 controls the time constant of the low-pass filter formed by the components 702, 704 and 706, and thus the duty cycle of the clock signal, based on the difference between the voltages on the intermediate nodes 714. and 720. In particular, the resistance of the RC filter is controlled by the voltage applied by the integrator 708 to the gate of the transistor 704, and the capacitance is controlled by the voltage applied by the integrator 708 to the capacitor 706. The FIG. 8 illustrates the voltage integrator 708 of FIG. 7 in more detail according to an exemplary embodiment.
    [0014] Integrator 708 comprises, for example, a current mirror having a reference branch formed by a series connection of transistors 802 and 804 coupled between VDD and ground, and another branch formed by a series connection of transistors 806 and 808. coupled between VDD and the mass. The transistors 804 and 808 respectively receive on their control nodes the signals IN + and IN- supplied respectively by the intermediate nodes 714 and 720 of FIG. 7. The control nodes of the transistors 802 and 806 are coupled together, and at a intermediate node between the transistors 802 and 804. An intermediate node 822 between the transistors 806 and 808 provides the output of the integrator 708, and is for example coupled to ground via a capacitor 824. Optionally, Calibration circuits 810 and 812 are respectively provided between transistors 802 and 806 and supply voltage V DD, and between transistors 804 and 808 and ground. For example, the circuit 810 comprises a PMOS transistor 814 coupled via its main conduction nodes between the transistor 802 and the supply voltage VDD, and a transistor 816 coupled by its main conduction nodes between the transistor 806 and VDD. Transistors 814 and 816 are for example controlled by a voltage V CALIB. Similarly, the circuit 812 includes, for example, an NMOS transistor 818 coupled between the source of the transistor 804 and the ground, and an NMOS transistor 820 coupled between the source of the transistor 808 and the ground. Transistors 818 and 820 are for example controlled by the calibration voltage V In operation, the transistor 806 will pass a current based on the input signal IN +, while the transistor 808 will pass a current based on on the input signal IN-. Therefore, any discrepancy between the IN + and IN- voltages on the nodes 714 and 720 will cause a current difference between the currents flowing in the transistors 806 and 808, and thus a residual current on the output node 822 causing a change. in the voltage stored by the capacitor 824. By adjusting the calibration voltage V CALIBi compensation can be provided for any discrepancy between the components so that the duty cycle of the clock signal is well balanced. An advantage of the circuit of Figure 8 is that it operates properly in DC conditions, and that its consumption is very low. An advantage of the embodiments described herein is that the optical receiver has a relatively low power consumption while allowing the reception of a low power optical signal. With the description thus made of at least one illustrative embodiment, various alterations, modifications and improvements will readily occur to those skilled in the art.
    [0015] For example, it will be apparent to those skilled in the art that embodiments have been described based on MOS transistors, and that alternative embodiments could be at least partially based on other embodiments. 5 transistor technologies such as bipolar technology. In addition, the manner in which the positive power rail and the negative power rail could be permuted in the various embodiments will be apparent to those skilled in the art, and rather than a ground voltage, a level 10 different supply voltage could be used as the negative voltage. In addition, it will be apparent to those skilled in the art that the various elements described in connection with the various embodiments could be combined, in alternative embodiments, in any combinations.
    权利要求:
    Claims (15)
    [0001]
    REVENDICATIONS1. Optical receiver of an optical link, comprising: a photodiode (202) coupled between a detection node (204) and a first supply voltage rail (GND), the photodiode being adapted to receive an optical clock signal including pulses; a switch (206) coupled between the detection node (204) and a second power supply voltage (VDD) rail; and a first transistor (211) coupled by its main conduction nodes between the second supply voltage rail (VDD) and a first output node (212) and having its control node coupled to the detection node (204) wherein the switch (206) is controlled based on a voltage on the first output node (212). 15
    [0002]
    An optical receiver according to claim 1, wherein the switch (206) is coupled to the second supply voltage rail (VDD) through a voltage shifter (208).
    [0003]
    The optical receiver of claim 2, wherein the voltage shifter is a diode-connected transistor (208).
    [0004]
    An optical receiver according to any one of claims 1 to 3, further comprising a second transistor (213) coupled by its main conduction nodes between the first output node (212) and the first supply voltage rail. (GND) and having its control node coupled to the detection node (204).
    [0005]
    An optical receiver according to any of claims 1 to 3, wherein the first output node 212 is coupled to the first supply voltage rail (GND) through the series connection of one or more several other switches (602, 604) controlled by a clock duty cycle control signal (OS). 3033220 B14065 - DD16082ST 19
    [0006]
    An optical receiver as claimed in claim 5, wherein the series connection of one or more other switches (602, 604) is coupled to the first supply voltage (GND) rail via a connected cable. diode (606).
    [0007]
    The optical receiver of another transistor according to any one of claims 1 to 6, further comprising: a low pass filter (404, 406, 614, 616) coupled to the first output node (212); and a comparator (402, 610) adapted to control the switch (206) based on a comparison between an output voltage of the low pass filter (404, 406) and a threshold level (VTHRESH, VTH)
    [0008]
    The optical receiver of claim 7, wherein the low-pass filter (404, 406) comprises at least one of: a variable resistor (614, 702, 704); and a variable capacitor (616, 706).
    [0009]
    An optical receiver according to claim 7, wherein the low-pass filter is an RO (resistor capacitance) filter comprising a resistor (702) and a transistor (704) coupled in parallel between the first output node and an intermediate node (608), and a variable capacitor (706), consisting of a transistor gate, coupled to the intermediate node (608).
    [0010]
    An optical receiver according to any one of claims 7 to 9, wherein the threshold voltage (V THRESH) is generated by a duty cycle control circuit adapted to adjust the duty cycle of the clock signal. 30
    [0011]
    An optical receiver according to any one of claims 7 to 9, wherein the comparator (402, 610) is implemented by an inverter (610), the threshold level being the threshold voltage of the inverter.
    [0012]
    An optical receiver according to any one of claims 7 to 11, further comprising a sequence of one or more inverters (214, 216, 218) coupled to the first output node and providing the signal of the present invention. 'clock.
    [0013]
    An optical receiver according to claim 12, further comprising a duty cycle detecting circuit comprising: a first low pass filter (710, 712) coupled to the output of a first inverter (214) of the sequence of inverters; a second low-pass filter (716, 718) coupled to the output of a second inverter (218) of the inverter sequence, the outputs of the first and second inverters being separated by an odd number of inverters of the sequence inverters; and a voltage integrator (708) adapted to generate an output voltage as a function of a voltage difference between the output voltages of the first and second low-pass filters, the voltage integrator (708) being adapted to control the RC value of the low-pass filter (404, 406, 614, 616).
    [0014]
    An optical receiver according to claim 13, wherein the voltage integrator (708) comprises a current mirror comprising: a first branch (802, 804) passing a first current based on the output voltage of the first pass filter down and a second branch (806, 808) comprising a second transistor (806) passing a second current based on the first current, and a third transistor passing a third current based on the output voltage of the second low pass filter, an intermediate node (822) between the second and third transistors providing the output voltage of the voltage integrator (708). 30
    [0015]
    A method of receiving a clock signal over an optical link, comprising: receiving, by a photodiode (202) coupled between a sense node (204) and a first supply voltage rail (GND), a optical clock transmission signal; and controlling a switch (206), coupled between the sense node (204) and a second power supply voltage (VDD) rail, based on a voltage on a first output node (212). ), the first output node (212) being coupled by the main conduction nodes of a first transistor (211) to the second supply voltage rail (VDD) and having its control node coupled to the sense node (204). ).
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    EP3182617A1|2017-06-21|Optical receiver comprising a relative phase detector
    FR3034593A1|2016-10-07|
    EP3945674A1|2022-02-02|Voltage converter
    FR3006833A1|2014-12-12|CIRCUIT AND METHOD FOR SIGNAL CONVERSION
    同族专利:
    公开号 | 公开日
    EP3062454B1|2018-10-17|
    EP3062454A1|2016-08-31|
    US10419833B2|2019-09-17|
    FR3033220B1|2017-03-10|
    US20160255425A1|2016-09-01|
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    法律状态:
    2016-02-25| PLFP| Fee payment|Year of fee payment: 2 |
    2016-09-02| PLSC| Search report ready|Effective date: 20160902 |
    2017-02-28| PLFP| Fee payment|Year of fee payment: 3 |
    2018-02-26| PLFP| Fee payment|Year of fee payment: 4 |
    2019-10-25| ST| Notification of lapse|Effective date: 20191006 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1551697A|FR3033220B1|2015-02-27|2015-02-27|OPTICAL BINDING CLOCK RECEIVER|FR1551697A| FR3033220B1|2015-02-27|2015-02-27|OPTICAL BINDING CLOCK RECEIVER|
    EP16155581.8A| EP3062454B1|2015-02-27|2016-02-12|Optical link clock receiver|
    US15/048,915| US10419833B2|2015-02-27|2016-02-19|Optical link clock receiver|
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